時 間 : 民國97年5月20日 星期二
地 點 : Ballrooms, 新竹國賓飯店10樓 (電話: 03-5151111,住址: 新竹市中華路二段188號)
Attend a FREE Synopsys Design Implementation/Verification seminar to learn more about the newest trends, technologies and methodologies that will enable you to deliver the best products to your customers with predictable success. The seminar includes two tracks. Track A introduces Synopsys’ Galaxy Design Platform new development and Track B is Synopsys' Discovery™ Verification Platform.
The Implementation Track (Track A) provides a forum for members of the electronic design community to learn more about the latest developments within the Galaxy™ Design Platform, and how to utilize these new capabilities effectively to increase design implementation productivity while achieving your performance, area, and manufacturability goals. We will also cover advancements in RTL synthesis, DFT, design planning, place-and-route, timing, and signal integrity analysis and sign-off.
The Verification Track (Track B) delivers the latest functional, AMS, system-level, and low-power verification methodologies while speeding closure, improving productivity, and reducing risk. Intended for verification engineers and managers, these technical sessions will also focus on the latest trends in system-to-silicon verification that will ensure your design success.
報名方法 : 請於5月15日前填妥報名表, 回覆至 snps_tw_seminar@synopsys.com
贈獎辦法 : 凡詳細填妥問卷即致贈精美禮品乙份,並有機會摸中大獎!
活動完全免費，座位有限，請即刻報名！
若報名額滿或現場報名來賓, 恕不保證座位及午餐!
聯 繫 : 台灣新思科技有限公司 (Synopsys Taiwan Limited)
(聯絡人: 02-23453020 分機: 0, 卓小姐)
報 到 : 活動當天上午 9: 00 – 9:30, 請準備兩張名片以完成報到
地 點 : Ballrooms, 新竹國賓飯店10樓 (電話: 03-5151111,住址: 新竹市中華路二段188號)
Attend a FREE Synopsys Design Implementation/Verification seminar to learn more about the newest trends, technologies and methodologies that will enable you to deliver the best products to your customers with predictable success. The seminar includes two tracks. Track A introduces Synopsys’ Galaxy Design Platform new development and Track B is Synopsys' Discovery™ Verification Platform.
The Implementation Track (Track A) provides a forum for members of the electronic design community to learn more about the latest developments within the Galaxy™ Design Platform, and how to utilize these new capabilities effectively to increase design implementation productivity while achieving your performance, area, and manufacturability goals. We will also cover advancements in RTL synthesis, DFT, design planning, place-and-route, timing, and signal integrity analysis and sign-off.
The Verification Track (Track B) delivers the latest functional, AMS, system-level, and low-power verification methodologies while speeding closure, improving productivity, and reducing risk. Intended for verification engineers and managers, these technical sessions will also focus on the latest trends in system-to-silicon verification that will ensure your design success.
報名方法 : 請於5月15日前填妥報名表, 回覆至 snps_tw_seminar@synopsys.com
贈獎辦法 : 凡詳細填妥問卷即致贈精美禮品乙份,並有機會摸中大獎!
活動完全免費，座位有限，請即刻報名！
若報名額滿或現場報名來賓, 恕不保證座位及午餐!
聯 繫 : 台灣新思科技有限公司 (Synopsys Taiwan Limited)
(聯絡人: 02-23453020 分機: 0, 卓小姐)
報 到 : 活動當天上午 9: 00 – 9:30, 請準備兩張名片以完成報到
