Silicon Image, Inc., a leader in semiconductors and intellectual property (IP) for the secure distribution, presentation and storage of high-definition (HD) content, today announced the newest member of its IP core family, the cineramIC™ 4K and 3D H.264 digital video decoder. With its high performance, low cost and high-quality video imaging, the cineramIC IP core can be integrated into System-on-Chips (SoCs) for next-generation digital TV (DTV), set-top-box (STB) and camcorder applications, as well as professional video editing, broadcast, medical and surveillance FPGA applications.
While consumer HDTVs are now prevalent worldwide, 3D video capability is gaining momentum in movie theaters and emerging in the consumer DTV market. The commercialization of ultra-high definition (UHD) resolutions is also on the horizon given the latest availability of professional 4K resolution cameras and displays.
“UHD formats such as 4K x 2K have four times the resolution of current high-definition TVs,” said Michelle Abraham, principal analyst with market research firm In-Stat. “While higher UHD resolution cameras and displays may be further off into the future, 4K resolution cameras and displays are already available for professional applications. It’s just a matter of time before 4K movie and camcorder content is available for professional consumer (prosumer) 4K displays.”
The cineramIC IP core is a high-performance, cost-effective multi-standard digital video decoder design with the following features:
Performance of up to 4K x 2K at 30 frames per second or high-definition 1080p 3D at 60 frames per second utilizing a single video pipeline implementation.
Support for H.264, MPEG-1/2 and VC-1 decoding.
Fully automatic multi-stream decoding for up to 16 streams, error detection and concealment, with very low software processing requirements.
H.264 Multiview Video Coding (MVC) extension support for multi-camera 3D, surveillance and sports viewing applications.
JPEG decoding of images up to 16K x 8K size with a decoding rate of 9 pictures per second for 32 Megapixel pictures.
“For over a decade, Silicon Image has been delivering high-performance and cost-effective MPEG and H.264 digital video decoders into the marketplace for use primarily in consumer applications,” said Ron Richter, director of business development at Silicon Image, Inc. “The cineramIC IP core family will help our SoC customers in future-proofing their consumer video ASIC products and also extend the reach of our IP products into the professional camera, broadcast, medical and security markets through our FPGA offerings.”
The cineramIC technology is designed to support HD, 3D, 4K and higher resolution video decoding functions. A 4K (4K x 2K) resolution digital video decoder SoC using the cineramIC IP core running at 30 frames per second will require about 970k ASIC gates to implement with a minimum clock speed of only 300MHz. This implementation can decode compressed video streams of up to 160 mega bits per second (maximum average CABAC performance), with the ability to decode even the most difficult professional video streams.
FPGA implementations will use a lower clock speed and require additional gates to implement. Fewer than 2 million instructions per second (MIPS) of CPU time is required to decode 4K video streams, making the cineramIC IP core one of the industry’s highest performing, most efficient video decoders in the world. Similar hardware and software resources are required for decoding high-definition 1080p 3D 60 frames per second video content.
Silicon Image’s cineramIC IP core also supports multi-channel video decoding, including the latest H.264 Multiview Video Coding (MVC) extension. Up to 16 video streams can be automatically decoded without software intervention, reducing implementation complexity and improving time-to-market for 3D, surveillance and broadcast applications.
Silicon Image’s family of IP cores also includes a broad range of HDMI® technology solutions, including transmitters and receivers incorporating HDMI Specification Version 1.4 features, Silicon Image’s Mobile High-Definition Link (MHL™) technology, Serial ATA storage (SATA) and camera image signal processors for mobile phone and netbook applications.
To see a live demonstration of the cineramIC IP core using an Altera Stratix IV GX FPGA board, visit us during the 2010 International CES, January 7-10, 2010 at the MGM Grand Hotel in Las Vegas. For editors and market analysts interested in meeting with Silicon Image during CES, please contact Sherrie Gutierrez at sherrie.gutierrez@siliconimage.com.
While consumer HDTVs are now prevalent worldwide, 3D video capability is gaining momentum in movie theaters and emerging in the consumer DTV market. The commercialization of ultra-high definition (UHD) resolutions is also on the horizon given the latest availability of professional 4K resolution cameras and displays.
“UHD formats such as 4K x 2K have four times the resolution of current high-definition TVs,” said Michelle Abraham, principal analyst with market research firm In-Stat. “While higher UHD resolution cameras and displays may be further off into the future, 4K resolution cameras and displays are already available for professional applications. It’s just a matter of time before 4K movie and camcorder content is available for professional consumer (prosumer) 4K displays.”
The cineramIC IP core is a high-performance, cost-effective multi-standard digital video decoder design with the following features:
Performance of up to 4K x 2K at 30 frames per second or high-definition 1080p 3D at 60 frames per second utilizing a single video pipeline implementation.
Support for H.264, MPEG-1/2 and VC-1 decoding.
Fully automatic multi-stream decoding for up to 16 streams, error detection and concealment, with very low software processing requirements.
H.264 Multiview Video Coding (MVC) extension support for multi-camera 3D, surveillance and sports viewing applications.
JPEG decoding of images up to 16K x 8K size with a decoding rate of 9 pictures per second for 32 Megapixel pictures.
“For over a decade, Silicon Image has been delivering high-performance and cost-effective MPEG and H.264 digital video decoders into the marketplace for use primarily in consumer applications,” said Ron Richter, director of business development at Silicon Image, Inc. “The cineramIC IP core family will help our SoC customers in future-proofing their consumer video ASIC products and also extend the reach of our IP products into the professional camera, broadcast, medical and security markets through our FPGA offerings.”
The cineramIC technology is designed to support HD, 3D, 4K and higher resolution video decoding functions. A 4K (4K x 2K) resolution digital video decoder SoC using the cineramIC IP core running at 30 frames per second will require about 970k ASIC gates to implement with a minimum clock speed of only 300MHz. This implementation can decode compressed video streams of up to 160 mega bits per second (maximum average CABAC performance), with the ability to decode even the most difficult professional video streams.
FPGA implementations will use a lower clock speed and require additional gates to implement. Fewer than 2 million instructions per second (MIPS) of CPU time is required to decode 4K video streams, making the cineramIC IP core one of the industry’s highest performing, most efficient video decoders in the world. Similar hardware and software resources are required for decoding high-definition 1080p 3D 60 frames per second video content.
Silicon Image’s cineramIC IP core also supports multi-channel video decoding, including the latest H.264 Multiview Video Coding (MVC) extension. Up to 16 video streams can be automatically decoded without software intervention, reducing implementation complexity and improving time-to-market for 3D, surveillance and broadcast applications.
Silicon Image’s family of IP cores also includes a broad range of HDMI® technology solutions, including transmitters and receivers incorporating HDMI Specification Version 1.4 features, Silicon Image’s Mobile High-Definition Link (MHL™) technology, Serial ATA storage (SATA) and camera image signal processors for mobile phone and netbook applications.
To see a live demonstration of the cineramIC IP core using an Altera Stratix IV GX FPGA board, visit us during the 2010 International CES, January 7-10, 2010 at the MGM Grand Hotel in Las Vegas. For editors and market analysts interested in meeting with Silicon Image during CES, please contact Sherrie Gutierrez at sherrie.gutierrez@siliconimage.com.
