瑞薩電子推出新32位元車用微控制器鎖定入門至中階等級汽車儀表總成應用

176-pin
R7F701404
R7F701424
R7F701405
R7F701425

272-pin
R7F701406
R7F701426
R7F701407
R7F701427

376-pin
R7F701408
R7F701428
R7F701410
R7F701430

484-pin
R7F701411
R7F701431
R7F701412
R7F701432

CPU

CPU System

RH850G3M

CPU Frequency

160 MHz

240 MHz

Memory Protection Unit (MPU)

Supported

Floating Point Unit (FPU)

Supported

Memory caches

Instruction cache

8 KB / 4-way associative

Non-CPU system memories

16 KB / 4-way associative

32 KB / 4-way associative

Memory

Code Flash

3.75 MB (R7F701404, R7F701424)
5 MB (R7F701405, R7F701425)

3.75 MB (R7F701406, R7F701426)
5 MB (R7F701407, R7F701427)

3.75 MB (R7F701408, R7F701428)
5 MB (R7F701410, R7F701430)

3.75 MB (R7F701411, R7F701431)
5 MB
(R7F701412, R7F701432)

Data Flash

64 KB

Local RAM

512 KB

Retention RAM

16 KB

Video RAM with Video RAM wrapper

1.55 MB

2 x 1.55 MB

External memory interfaces

SDRAM Interface

Bus width

-

32-bit

16-bit

32-bit

Mode

-

SDR-SDRAM (SDRA)

DDR2-SDRAM Interface (SDRB)

Max. clock

-

80 MHz

240 MHz

Serial Flash Memory Interface

Bus width

8-bit

Mode

SDR, DDR

Max. clock

SDR : 120 MHz, DDR : 80 MHz

DMA

16 channels

Operating clock

Main Oscillator

8 to 16 MHz

Low Speed Internal Oscillator

Typ. 240 kHz

High Speed Internal Oscillator

Typ. 8 MHz

Sub Oscillator

Typ. 32.768 kHz

Spread-spectrum PLL0

480 MHz

PLL1

Fixed to 480 MHz

PLL2

-

Max. 480 MHz

I/O port

126

126

159

199

A/D converter

16 channels, 12 bit resolution

20 channels, 12 bit resolution

Timer

16-bit Timer Array Unit B (TAUB)

3 units (16 channels / unit)

32-bit Timer Array Unit J (TAUJ)

1 unit (4 channels / unit)

Timer for Operating System (OSTM)

2 units (32-bit resolution, 1 channel / unit)

32-bit Always-On-Area Timer (AWOT)

1 unit (1 channel / unit)

Real Time Clock (RTCA)

Supported

Window Watchdog Timer A (WDTA)

2 units

PWM Generators with Diagnostic

1 unit (12-bit resolution, 24 PWM generators, 12 with diagnostic capability)

Communication interface

Communication interface

Clocked Serial Interface G (CSIG)

4 channels

Queued Clocked Serial Interface H (CSIH)

2 channels

CAN Interface (RS-CAN)

3 channels (total 192 message buffers)

CAN Interface (RSCANFD)

3 channels (total 192 message buffers) : Only available for R7F701428, R7F701430, R7F701431, R7F701432

LIN / UART Interface (RLIN3)

4 channels

I²C Interface (RIIC)

2 channels

Ethernet AVB MAC (ETNB)

1 channel (Media Access Controller for up to 100 Mbps, with Audio Video Bridging)

Media Local Bus (MLBB)

-

1 channel (50 Mbps)

External interrupts

Maskable

11

Non-maskable (NMI)

1

Audio

Sound Generator (SG)

5 units

PCM-PWM Converter (PCMP)

1 unit

I²S Interface (SSIF)

2 units (1 channel / unit)

Video and Graphics

Video and Graphics

Video output (VO)

Channels

1 channel (1024 x 1024 pixels, 30 MHz pixel clock, RGB888,

4 layers)

2 channels (1024 x 1024 pixels, 48 MHz pixel clock, RGB888,

4 layers)

Interface

LVTTL

LVTTL for both channels, single RSDS selectable for channel 0 or 1

Pre-distortion

Warping Engine (VOWE)

Warping Engine (VOWE) for video channel 0

RLE decoding

Supported

Supported for each video channel

Sprite layer

3 x 16 sprites for 3 output layers

Timing Controller(TCON)

7 programmable signals

Video input(VI)

Channels

1 channel

1 channel

2 channels

Resolution

1024 x 1024 pixels

Pixel clock

30 MHz

60 MHz

Color formats

RGB666, ITU656

RGB888, ITU656

Interface

LVTTL

LVTTL for both channels, single MIPI CSI-2 for channel 0

Graphics Processing Unit

2D Graphics Processing Unit (GPU2D), 80 MHz operation clock

2D Graphics Processing Unit (GPU2D), 240 MHz operation clock

JPEG Unit (JCUA)

Supported

Video output data control

Video output data control

Video Output Checker (VOCA) 2 CRC checker (DISCOM)

Video Output Checker (VOCA) 2 CRC checker (DISCOM) for each video channel

Other functions

LCD Bus Interface (LCBI)

18 bit output, max. 10 MHz

-

Clock Monitors (CLMA)

For Main oscillator, Low speed internal oscillator, High speed internal oscillator, PLL0, PLL1, Video Input pixel clocks

Data CRC (DCRA)

Supported

Power-On-Clear (POC)

Supported

Intelligent Stepper Motor Driver (ISM), incl. zero point detection for each channel

1 unit,
6 channels

1 unit,
4 channels

1 unit,
6 channels

Error Correction Coding (ECC)

For Code Flash, Data Flash, Local RAM, Retention RAM, Video RAM, RS-CAN RAM, Caches tag / data RAMs

Intelligent Cryptographic Unit (ICU-S2)

Supported

On-Chip Debug (OCD)

Supported

Boundary Scan

Supported

Voltage supply

Internal logic

Always-On-Area

3.3 V, 5 V via on-chip voltage regulator

Isolated-Area

3.3 V, 5 V via on-chip voltage regulator

1.25 V

I/O buffers

GPIO

3.3 V, 5 V

SDR-SDRAM

-

3.3 V

-

DDR2-SDRAM

-

1.8 V

A/D Converter supplies

Nominal 3.3 V, 5 V

Package

HLQFP24 x 24
(0.5 mm)

BGA 21 x 21
(1.0 mm)

BGA 23 x 23
(1.0 mm)

BGA 27 x 27
(1.0 mm)